The present invention relates to a memory circuit and particularly to a memory circuit having a power-down mode in which power consumption is reduced in a non-selected state.
Access mode and stand-by mode of memory circuits are controlled by a chip selection signal. In access mode, peripheral circuits such as address decoders, output circuits are enabled as well as memory cells, and access operations to memory cells are conducted. In stand-by mode, power supply to a peripheral circuit is stopped while maintaining power supply to memory cells so that access to the memory cell is inhibited. This feature of the stand-by mode contributes to power reduction when the memory circuit is not accessed. In this sense, this stand-by mode is also referred to as "power-down mode".
In addition to the reduction of power consumption, many efforts have been paid to improve access time. Access time has been discussed in two categories. One is the so-called address access time which is the access time from a time point when address information to the memory circuit is established under the state that the memory circuit is enabled by a chip selection signal. The other is the so-called chip selection access time which is the access time from a time point when the memory circuit is switched to the enabled state by the chip selection signal while address information has been established prior to the enabled state.
In recent microcomputer systems, it has been routine to apply address information and a chip selection signal to a memory employed therein in such manner that address information is first applied to the memory and thereafter the memory is enabled by the chip selection signal. Therefore, access time to the memory is substantially determined by the chip selection access time. Thus, when a memory circuit is used in such a system, the chip selection access time has significance and is required to be faster than the address access time.
However, in conventional memory circuits, it has been difficult to achieve desired chip selection access time because the peripheral circuits of the memory circuit are changed from a non-powered state to a powered, enabled state a predetermined time after from the control of the chip selection signal. Thus, it has been difficult to provide a memory circuit which consumes less power in stand-by mode and simultaneously, has the feature that the chip selection access time is faster than the address access time.